Two Approaches to Optimizing for Power in the Spiral Framework

This paper evaluates two methods for generating power or energy optimized Digital Signal Processing (DSP) transforms. Both approaches integrate power models into the SPIRAL code generator. SPIRAL decomposes a transform into an algorithmic formula representation, which is then implemented in C and timed. The timing data is used as feedback to control the parameters of the next algorithm generated. By replacing the timing method with power estimation models, we direct SPIRAL to search for a poweroptimized implementation. We implement and evaluate two different methods: a processor simulator and power model, and a hardware based method that models power based upon data collected directly from on-chip Pentium 4 performance counters.